Multi CPU

Organization:

Arm Limited

Contact:

tf-m@lists.trustedfirmware.org

The following documents outline the design and implementation principles of TF-M for multi-cpu and hybrid platforms, where the Secure Processing Environment (SPE) and Non-secure Processing Environment (NSPE) execute on separate cores.

During boot, the secure core initializes the hardware and peripherals that the NSPE uses, establishing an assured execution path.

The cores communicate using a mailbox-based Inter-Processor Communication (IPC) mechanism.

The framework includes a Remote Procedure Call (RPC) layer and an NS Agent Mailbox to abstract platform dependencies. Hybrid platform scheduling extends the original dual-cpu concepts for systems with a local and multiple remote NSPEs, supporting flexible scheduling policies.

• Booting a multi-cpu
• Hybrid Platform Topology
• Mailbox Design
• Memory Access Check
• SPE - NSPE communication

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